DPW (Dies Per Wafer) is the number of chips a wafer can yield, determined by wafer diameter, die area and edge loss. The theoretical value follows a circular-area approximation; the actual count is lower because of incomplete edge dies, scribe lanes and test areas. Enter the wafer diameter and die size and the tool computes the theoretical DPW and an edge-loss-adjusted estimate - the input for yield-target breakdown and cost modeling during capacity ramp-up, helping management judge production scale and foundry pricing.
Yield models relate the defect density D0 to the die area A: the Poisson model Y = exp(-D0*A) is conservative; the Murphy model Y = [(1 - exp(-D0*A)) / (D0*A)]^2 fits real distributions better; binomial and seed models also exist. The tool includes several models so you can compare yield differences under different assumptions. Differences between models help identify the defect distribution shape and set quantified targets for defect-reduction projects.
Capacity and cost estimation before a new chip tape-out; foundry quotation and margin assessment; target setting for defect-density improvement; and yield/cost comparison of different die-size options. Model differences support defect-pattern identification, capacity ramp, delivery and inventory decisions, and give management a basis for judging production scale and foundry pricing. Inputs are simple and outputs are intuitive, making it easy to present yield scenarios in meetings and reports.
The tool outputs the theoretical/actual DPW, yield under each model, usable die count and the corresponding cost allocation. Use D0 from historical data at the same process node; a larger die area lowers yield and raises the edge-loss share. Yield models are estimates - final numbers come from measured WAT and final test data. Correct the results with scribe-lane width and edge-exclusion parameters so the theoretical values do not run high, and adjust for additional package and test losses for the final shipped yield.